In modern computer systems, it is common to have multiple processors both in the way of multiple cores of a multi-core processor, and in the way of multiple processor sockets, each potentially including multiple cores. In addition, other system components such as various semiconductor devices, e.g., I/O devices, controllers, chipsets and so forth are also present in a typical system. To enable the various components to interact with efficiency and commonality of data, many systems incorporate some type of cache coherency protocol. That is, many systems have a protocol in place to allow multiple copies of a given datum to be present in various locations of a system such as a system memory as well as one or more caches that can be associated with different components of the system.
Different cache coherency protocols exist. One common protocol implements a directory that is typically stored in system memory. This directory maintains information regarding the location and status of data present in the various caches or other structures of the system. To maintain coherency of the data and allow for accurate updating of state information, various communications occur according to this cache coherency protocol.
Because the directory is typically stored in memory, memory bandwidth is consumed by such cache coherency communications. This memory bandwidth consumption can negatively impact application performance, particularly m a multiprocessor system where data is shared by multiple components.